This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-316749, filed Oct. 17, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to a ferroelectric memory device.
More specifically, the present invention relates to a ferroelectric memory device in which nonvolatile properties of held data has been achieved by a ferroelectric material for a memory cell capacitor.
Conventionally, there has been developed a ferroelectric memory device employing a ferroelectric material for a memory cell capacitor. Such a ferroelectric memory device requires a shorter time for a write operation as compared with a nonvolatile flash memory. Additionally, the voltage and power consumption have advantageously been lowered. However, the following problems have arisen with a conventionally proposed ferroelectric memory device.
FIG. 17 shows an exemplary configuration of a conventional ferroelectric memory device having a 2T2C type cell structure. In the case of this ferroelectric memory device, a memory cell MC (per bit) include two MOS transistors (M) and two ferroelectric capacitors (C). Thus, there is a problem that a cell area is increased.
FIG. 18 shows an exemplary configuration of a conventional ferroelectric memory device having a 1T1C type cell structure. In the ferroelectric memory device, a memory cell MC (per bit) include one MOS transistor (M) and one ferroelectric capacitor (C). Thus, a memory cell area of this structure is smaller than a memory cell area of the above described 2T2C type cell structure. However, there has been a problem that a reference potential (RPL) is required, and its design is difficult.
In addition, a large capacity cell plate drive line (PL) is provided in a conventional ferroelectric memory device, thus requiring a large driver circuit for driving the cell plate drive line. Occasionally, the area of this driver circuit has consumed about 15% of the chip size.
In recent years, there is proposed a ferroelectric memory having a plurality of unit cells coupled in series (hereinafter, referred to as a TC parallel unit serial connection type ferroelectric memory device). Each unit cell is configured so as to couple electrodes at both ends of a capacitor (C) between a source and a drain of a cell transistor (T), respectively.
FIG. 19 shows an exemplary configuration (cell structure) of a conventional TC parallel unit serial connection type ferroelectric memory device. In the figure, the electrodes of the ferroelectric capacitor C are coupled to the source and drain of an NMOS transistor M, respectively, to configure a memory cell MC. Then, a configuration is provided such that a plurality of the memory cells MC are coupled in series.
However, in the TC parallel unit serial connection type ferroelectric memory device, a memory cell MC (for example, MC7 and MC7xe2x80x2), proximal to cell plate drive lines PL and /PL, has respective different antenna ratios at both ends of the ferroelectric capacitor C. That is, the wire length between memory cells MC7 and MC7xe2x80x2 and adjacent memory cells MC6 and MC6xe2x80x2 is in the order of micrometers. In contrast, the cell plate drive lines PL and /PL have wire lengths in the order of millimeters. Because of this, for example, if a high voltage static electricity is applied to the outside of a chip when the power is turned OFF, there occurs a difference in potential induced between both electrodes of the ferroelectric capacitor C of the memory cells MC7 and MC7xe2x80x2. As a result, a high voltage is temporarily applied to the ferroelectric capacitor C of the memory cells MC7 and MC7xe2x80x2, which could cause data destruction or lowered signal strength.
According to an embodiment of the present invention, there is provided a ferroelectric memory device comprising: a word line; first and second bit lines cross to the word line; a memory cell including a first transistor a gate of which is coupled to the word line and one of source and drain of which is coupled to the first bit line, a second transistor a gate of which is coupled to the word line and one of source and drain of which is coupled to the second bit line, and a ferroelectric cell capacitor coupled to the other of source and drain of the first and second transistor; and first and second capacitors each coupled via a switching transistor to a respective one of the first and second bit lines; wherein first and second voltages complementary to each other are applied to the first and second bit lines, via the first and second capacitors, respectively.
According to an embodiment of the present invention, there is provided a ferroelectric memory device, comprising a plurality of word lines, first and second bit lines cross to the plurality of word lines, cell blocks each including a plurality of memory cells coupled in series and each including a plurality of transistors whose gate is coupled to a respective one of the plurality of word lines, and a plurality of ferroelectric cell capacitors coupled between the source and drain of the plurality of transistors, respectively, one end of the series-coupled memory cells being coupled to the first bit line, and the other end thereof being coupled to the second bit line; and first and second capacitors coupled to the first and second bit lines, respectively, via a switching transistor, wherein first and second voltages complementary to each other are applied to the first and second bit lines via the first and second capacitors, respectively.
According to an embodiment of the present invention, there is provided a ferroelectric memory device, comprising a plurality of memory cells coupled in series and including a plurality of cell transistors whose gate is coupled to a respective one of a plurality of word lines and a plurality of ferroelectric cell capacitors coupled between the source and drain of the plurality of cell transistors, respectively, and wherein one end of the plurality of memory cells is coupled to a bit line, and the other end thereof is coupled to a plate line, the plurality of cell transistor being configured by a depression type NMOS transistor.
According to an embodiment of the present invention, there is provided a ferroelectric memory device, comprising a plurality of memory cells coupled in series and including a plurality of cell transistors whose gate is coupled to a respective one of a plurality of word lines and a plurality of ferroelectric cell capacitors coupled between the source and drain of the plurality of cell transistors, respectively, and wherein one end of the plurality of memory cells is coupled to a bit line, and the other end thereof is coupled to a plate line, the plurality of cell transistor being configured by a PMOS transistor.
According to an embodiment of the present invention, there is provided a ferroelectric memory device, comprising one end of a memory cell including a cell transistor and a ferroelectric cell capacitor coupled to the cell transistor being coupled to a bit line, and the other end thereof being coupled to a plate line, a protective transistor being provided between the other end of the memory cell and the plate line.
According to an embodiment of the present invention, there is provided a ferroelectric memory device, comprising a plurality of memory cells coupled in series and including a plurality of cell transistors whose gate is coupled to a respective one of a plurality of word lines and a plurality of ferroelectric cell capacitors coupled between the source and drain of the plurality of cell transistors, respectively, and wherein one end of the plurality of memory cells is coupled to a bit line, and the other end thereof is coupled to a plate line, a protective transistor being provided between the other end of the plurality of memory cells and the plate line.
According to an embodiment of the present invention, there is provided a ferroelectric memory device, comprising a plurality of memory cells coupled in series and including a plurality of cell transistors whose gate is coupled to a respective one of a plurality of word lines and a plurality of ferroelectric cell capacitors coupled between the source and drain of the plurality of cell transistors, respectively, and wherein one end of the plurality of memory cells is coupled to a bit line, and the other end thereof is coupled to a plate line, and an electrostatic barrier layer including an electrically conductive layer provided above the plurality of ferroelectric cell capacitors.
According to an embodiment of the present invention, there is provided a ferroelectric memory device, comprising a plurality of memory cells coupled in series and including a plurality of cell transistors whose gate is coupled to a respective one of a plurality of word lines and a plurality of ferroelectric cell capacitors coupled between the source and drain of the plurality of cell transistors, respectively, and wherein one end of the plurality of memory cells is coupled to a bit line, and the other end thereof is coupled to a plate line, and a plurality of electrostatic barrier layers each including an electrically conductive layer and provided above the plurality of ferroelectric cell capacitors.